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Announcements of Opportunity

SURF: Announcements of Opportunity

Below are Announcements of Opportunity posted by Caltech faculty and JPL technical staff for the SURF program.

Each AO indicates whether or not it is open to non-Caltech students. If an AO is NOT open to non-Caltech students, please DO NOT contact the mentor.

Announcements of Opportunity are posted as they are received. Please check back regularly for new AO submissions! Remember: This is just one way that you can go about identifying a suitable project and/or mentor. Click here for more tips on finding a mentor.

Announcements for external summer programs are listed here.

New for 2021: Students applying for JPL projects should complete a SURF@JPL application instead of a "regular" SURF application.

Students pursuing opportunities at JPL must be
U.S. citizens or U.S. permanent residents.

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Project:  FPGA Modernization
Disciplines:  Electrical Engineering and Computer Science, Computer Science
Mentor:  Daniel Nakamura, (JPL), Daniel.I.Nakamura@jpl.nasa.gov, Phone: (818) 354-5718
Background:  JPL FPGA designs are becoming larger and more complex. With more simultaneous projects to support and limited resources, design teams need a proven flow to meet schedule, control costs, and maintain quality.
Summary description:
- Implement proven design/verification techniques
- Validate system design early
- Design/verify at the highest level of abstraction
- Automate (Correct-by-construction) where ever possible
- Continually improve
Impacts / Benefits:
- Providing a common design/verification environment eliminates the learning curve from project-to-project and for engineering support across divisions
- Reuse shortens design cycles
- Leveraging fully verified IP improves the quality of designs
Description:  Create an institutional FPGA design and verification flow based on industry best practices
- Provide an IP library containing key modules used by 33x, 34x, and 38x
- Provide a flow allowing easy integration of IP into a system-on-chip
- Demonstrate a system architecture methodology provides early design validation and a path to implementation
- Demonstrate a verification methodology that is reusable from simulation to lab testing.
Student Requirements:  - Able to write scripts in: Python or Ruby
- Suggest having some know
Location / Safety:  Project building and/or room locations: . Student will need special safety training: .
Programs:  This AO can be done under the following programs:

  Program    Available To
       SURF    Caltech students only 

Click on a program name for program info and application requirements.


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