Project:	OUSW Evaluation of SEE in Space Computing Hardware (JPL AO No. 16847)
Disciplines:	Computer Science, Physics/Applied Physics
Mentor:	Steven Guertin, (JPL), Steven.M.Guertin@jpl.nasa.gov, Phone: (818) 393-6895
Background:	JPL supports the Office of the Under Secretary of War (OUSW) through evaluation of electronic components for the Trusted & Assured Microelectronics (T&AM) program, ensuring the reliability and mission success of spaceflight hardware. This is achieved by evaluating electronic components, materials, and manufacturing processes for use in the harsh environment of space. For space missions, particularly those operating in radiation-intensive environments, understanding how electronic parts respond to ionizing radiation is essential. OUSW is interested in development of methods to evaluate the radiation performance of modern, high-performance, computing hardware. As a summer intern working on this OUSW research, you will support ongoing radiation effects evaluation of next-generation radiation-hardened system on a chip (SOC) devices in addition to exploring similar sensitivity in commercial or automotive parts. This work directly informs part selection and qualification processes for government-sponsored missions and helps maintain a robust database of radiation response data, ensuring future projects have access to critical information when designing for high-reliability applications in space.
Description:	The selected intern will support radiation effects testing and analysis within JPL’s support of the OUSW T&AM program, with a focus on single event effects (SEE) characterization of SOCs and complex modern computing hardware. Interns will assist in the preparation of test campaigns, including selecting and handling parts, developing test plans, and configuring test hardware and software. Interns will collect and analyze SEE data, identify SEE, and compare results to expected radiation responses. Finally, interns will contribute to technical reporting, documenting procedures, data, and findings to support the government’s long-term parts reliability database and future mission design efforts. This project will provide interns with valuable experience in radiation effects research, spaceflight hardware qualification, and the critical intersection of electronics, physics, and data science.
References:	https://dataverse.jpl.nasa.gov/dataset.xhtml?persistentId=hdl:2014/45991 S.M. Guertin, "Guideline for Single-Event Effect (SEE) testing of System on a Chip (SOC) devices" - Feb 2018, JPL Open Repository
Student Requirements:	Required: Writing and deploying code for a modern computing architecture (GPU, Multi-threaded, or other hardware-aware computer programming); knowledge of running “lower-level code” (C/C++/benchmarking or compute-intensive code) to evaluate performance of hardware under Linux, data reduction/parsing (e.g. Python, Matlab, etc.); writing/communication skills; Ability to travel. Desired: Knowledge of general support equipment - power supplies, oscilloscopes, SMUs, etc.
Location / Safety:	Project building and/or room locations: . Student will need special safety training: .
Programs:	This AO can be done under the following programs:   Program    Available To        SURF@JPL    both Caltech and non-Caltech students  Click on a program name for program info and application requirements.